1. Field of the Invention
The present invention relates to a pixel structure of a thin film transistor (TFT) array substrate, and more particularly to a pixel structure for lowering a parasitic capacitance formed between a first metal layer and a second metal layer.
2. Description of Related Art
The rapid development of semiconductor devices and display panels contributes to the quantium leap for a multimedia society. Take the display for an example. A cathode ray tube (CRT) has enjoyed the monopoly in the display market due to its low cost and superior display quality. However, the CRT fails to follow the current trends because of low-power consumption, bulky volume (i.e. high compactness) and so forth. Therefore, a TFT liquid crystal display (TFT-LCD) has replaced the CRT and become the mainstream product in the display market because of its superior display quality, high compactness, low-power consumption, and free-radiation safety.
The TFT-LCD comprises a thin film transistor (TFT) array substrate, a color filter substrate and a liquid crystal layer, wherein the TFT array substrate further includes a plurality of arrayed TFTs and pixel electrodes disposed to correspond to each TFT, respectively. Additionally, the arrayed TFTs are used as the switching element for turning on its corresponding liquid crystal display unit, respectively. Additionally, for controlling each individual pixel, a certain scan line and a certain data line are selected to turn on a certain pixel to display in accordance with supplied display data through enabling these certain scan lines and data lines.
FIG. 1 shows a top view of a conventional pixel structure of a TFT array substrate. FIG. 2 is a cross-sectional view of the conventional pixel structure of the TFT array substrate, providing the cut-open view of the line I-I′ shown in FIG. 1. Referring to FIGS. 1 and 2, the conventional pixel structure 100 of the TFT array substrate comprises a substrate 110, a first metal layer 120, a dielectric layer 130, a semiconductor layer 140, a second metal layer 150, a protection layer 160 and a pixel electrode 170. The first metal layer 120, disposed on the substrate 110, comprises a gate 122 and a scan line 124 electrically thereto. The dielectric layer 130, covered by the semiconductor layer 140 and disposed on the substrate 110, covers the first metal layer 120 including the gate 122. The second metal layer 150 comprises a source/drain 152/154, disposed on the semiconductor layer 140, which partially overlaps the gate 122, and a data line 156, which electrically connects to the source 152 and partially overlaps the scan line 124. In addition, the protection layer 160, disposed on the substrate 110, overlaps the first metal layer 120 and the second metal layer 150. The protection layer 160 comprises an opening 162 for exposing the drain 154, wherein the pixel electrode 170 electrically connects to the drain 154 through the opening 162 of the protection layer 160.
In the conventional pixel structure 100, the first metal layer 120 and the second metal layer 150 are partially overlapped, so as a parasitic capacitance is produced in the overlapped location thereof. In other words, the parasitic capacitance occurs between the gate 122 and the source/drain 152/154 and the area between the scan line 124 and the data line 156, so that the parasitic capacitance affects the pixel's voltage causes a signal distortion and the display quality of the LCD degrades.